1. Field of the Invention
This invention relates generally to a semiconductor integrated circuit device and a method for fabricating the same. More particularly, the present invention relates to an improved NAND logic gate circuit for use in microprocessors and a method of fabricating the NAND circuit so as to be capable of operating at higher speeds.
2. Description of the Prior Art
It is generally known that the design and fabrication of microprocessors have become a very competitive business. At present, it is also well-known that increasing the speed by 10% in the microprocessor design will typically provide a 40% increase in profitability. As a consequence, there exists a continuing challenge to microprocessor designers to increase the speed of microprocessors but yet maintaining a relatively low leakage current in order to operate at a low power consumption.
Heretofore, there have been encountered various prior art techniques which are commonly used to increase the speed of microprocessors and are listed as follows:
(1) Increasing of the DC power supply potential.
(2) Reducing the effective channel length of CMOS devices.
(3) Reducing or lowering the threshold voltage of the CMOS devices.
Thus far, it appears that the most effective way of boosting the speed performance in the microprocessor design is through the channel length reduction. However, there are certain limitations and design penalties in the process of continually reducing of the channel length. For example, there will be decreased the amount of current driving capability when the sizes of the devices are scaled-down. In addition, a larger amount of leakage current will occur, due to the reduction of channel length, which may create serious problems in chip design and application.
The inventor has realized that there exists another technique, besides the channel length reduction, in which to substantially improve the CMOS transistor speed. This new technique is achieved by the reduction of overlap capacitance, which thus far has not been considered by anyone to the knowledge of the inventor. As a background and in order to assist in the understanding of the present invention, there is shown in FIG. 1 a cross-sectional view of a MOS transistor 102 which includes a source region 104 and a drain region 106 formed on a surface of a silicon substrate 108. A gate oxide film 110 is formed on the substrate between the source and drain regions. A gate electrode 112 is formed on the surface of the gate oxide film 110. As can be seen, the overlap capacitance C.sub.OV on the source side is defined to be equal to the overlapping capacitance C.sub.OV1 between the gate and the source plus the fringing capacitance C.sub.OV2 between the edge of the gate and the source. Similarly, the overlap capacitance C.sub.OV on the drain side is defined to be equal to the overlapping capacitance C.sub.OV1 between the gate and the drain plus the fringing capacitance C.sub.OV2 between the edge of the gate and the drain.
In FIG. 2, there is shown a top plan view of the MOS transistor 102 of FIG. 1 so as to better illustrate the areas where the overlap capacitances are formed. In particular, the source region 104 has a width W and a length Y.sub.s. The drain region 106 has also a width W and a length Y.sub.d. The gate electrode 112 has also a width W and a length L'. Further, the (effective) channel length is L, the source overlap length is L.sub.s, and the drain overlap is L.sub.d. Thus, the overlapping capacitance C.sub.OV1 on the source side is measured between area 114 and area 116, and the fringing capacitance C.sub.OV2 is measured between the edge of the area 114 adjacent the channel and the area 116. Similarly, the overlapping capacitance C.sub.OV1 on the drain side is measured between area 118 and area 120, and the fringing capacitance C.sub.OV2 is measured between the edge of the area 118 adjacent the channel and the area 120.
It should be understood that by decreasing the channel length L the overlap capacitance C.sub.OV on both the source and drain sides will be increased, if the gate, source and drain dimensions are maintained, which will adversely effect the operation of the transistor by increasing the RC delay time. Also, as the devices being scaled-down, the overlap capacitance will become more and more critical and influential on the speed performance. This is due to the fact that the percentage of the overlap capacitance including the fringing capacitance to the total gate capacitance will become larger and thus plays a more dominant role in the speed performance. Therefore, there still exists a need of developing an improved device structure which will have CMOS transistors having both channel length reduction and overlap capacitance reduction.
Since NAND logic gate circuits are considered to be the basic building block used in microprocessor design, the inventors of the present invention conducted a study of the speed performance on ring oscillators in the 3-input NAND inverter circuit of the type as shown in FIG. 3 and labeled "Prior Art" which are connected to each other in multiple stages. As a result of the investigation about the relationship between the P-channel and N-channel transistors having shorter channel lengths and the overlap capacitance reduction, the inventor has discovered a way of fabricating a faster NAND logic gate circuit for use in microprocessor designs which has higher speeds of operation.
Moreover, according to the fabrication process of the invention, the NAND logic gate circuit can be manufactured by utilizing the same "nominal sub-micron" CMOS fabrication technology so that existing equipment is used and no investment in new equipment is necessitated, thereby avoiding any increase in manufacturing costs. As used herein, the term "nominal sub-micron" refers to a quarter-micron process where the channel length is 0.25 .mu.m. The term "sub-nominal" means smaller than the nominal sub-micron.